In high-speed ADC applications, as well as in every other instance when sampling of an analog signal is involved (i.e. optical receivers, data stream “slicers”, etc.), the precision of the sampling instant impacts the signal-to-noise ratio (SNR) of the discrete-time signal fed into the system. Accordingly, the stability of the timing reference is of paramount importance. From the 12-bit level accuracy on, the thermal noise contribution to SNR has to be minimized to such an extent that a noise contribution coming from sampling jitter of 1 ps or higher becomes the limiting factor for SNR—at least from 70 MHz input frequency on.
A very clean time reference (OCXO, or other crystal-based solution, further band-pass filtered) must be provided to the non-overlapped phase generation circuits. In turn, the on-chip circuits must provide a clean transition edge to the sampling device—usually a simple switch—driven through a carefully optimized, short path within the clock distribution tree. The thermal noise of the logic gates, and especially the voltage bounce of the supply rails, can significantly degrade the stability of the clock period, introducing perturbations on the time of occurrence of the sampling edge which are inversely proportional to the slope of the waveforms featured at every node.